1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device for performing an address training operation, and a system including the same.
2. Description of the Related Art
In a high speed semiconductor device, an address is inputted at a speed twice as fast as that of a clock. Accordingly, a new operation called an address training operation has been introduced. According to this operation, a chipset sends a first address to a semiconductor device, the semiconductor device outputs a second address based on the first address to the chipset again, and the chipset checks whether the first address coincides with the second address, thereby finding an area where the address is normally recognized.
In the address training operation, data for training an address, which are generated in an address training driver, are first outputted at an output pin near the address training driver as compared with an output pin remote from the address training driver. Therefore, skew occurs between the pins. Furthermore, in the address training operation between the chipset and the semiconductor device, since it is necessary to change an output timing of data according to output pins, a time required for the address training operation may increase, resulting in the deterioration of performance.